DMACR

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Interpret as DMACR

SSP0 DMA control register

RXDMAE	Receive DMA Enable. When this bit is set to one 1, DMA for the receive FIFO is enabled, otherwise receive DMA is disabled.
TXDMAE	Transmit DMA Enable. When this bit is set to one 1, DMA for the transmit FIFO is enabled, otherwise transmit DMA is disabled
RESERVED	Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.

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